As is well known to those of skill in the art, conventional semiconductor memory devices include a memory cell array region and a peripheral circuit region. The memory cell array region typically includes a plurality of memory cells, local sense amplifiers, local data I/O lines and global data I/O lines. The peripheral circuit region typically includes an I/O sense amplifier and a write driver. The global data I/O line in the memory cell array region is used during both a read operation and a write operation.
FIG. 1 is a schematic view illustrating the structure of a local data I/O line and a global data I/O line of a conventional semiconductor memory device.
In FIG. 1, reference numerals 10 and 20 denote a memory cell array region and a peripheral circuit region, respectively. LIO and LIOB denote a local data I/O line pair, GIO and GIOB denote a global data I/O line pair, RDIO and RDIOB denote a read data line pair, WDIO and WDIOB denote a write data line pair, LSA denotes a local sense amplifier, LGIOG denotes a local global I/O gate, DRV denotes a write driver, and IOSA denotes an I/O sense amplifier. The local global I/O gate LGIOG includes two transistors TR. The function and operation of the components of FIG. 1 are as follows.
During a read operation, the local sense amplifier LSA of the memory cell array region 10 amplifies a data signal of the local data I/O line pair LIO/LIOB and transmits it to an I/O sense amplifier IOSA in the peripheral circuit region 20 through the global data I/O line pair GIO/GIOB. The I/O sense amplifier IOSA amplifies the data signal transmitted through the global data I/O line pair GIO/GIOB and outputs it to the read data line pair RDIO/RDIOB. Likewise, during a write operation, the write driver DRV drives a data signal received through the write data line pair WDIO/WDIOB and outputs it to the global data I/O line pair GIO/GIOB. The data signal is provided to the local global I/O gate LGIOG via the global data I/O line pair GIO/GIOB, and the local global I/O gate LGIOG transmits this data signal to the local data I/O line pair LIO/LIOB.
In summary, during a read operation, the semiconductor memory device of FIG. 1 uses the local sense amplifier LSA to amplify a data signal carried by the local data I/O line pair LIO/LIOB. This amplified data signal is then transmitted to the peripheral circuit region 20 through the global data I/O line pair GIO/GIOB. During a write operation, the write driver DRV is used to drive a data signal carried by the write data line pair WDIO/WDIOB. This data signal is then transmitted through the global data I/O line pair GIO/GIOB to the local data I/O line pair LIO/LIOB of the memory cell array region 10 through the local global I/O gate LGIOG.
FIG. 2 is a circuit diagram illustrating the local sense amplifier and the local global I/O gate of the conventional semiconductor memory device of FIG. 1. The local sense amplifier LSA includes five transistors TR1 to TR5, and the local global I/O gate includes two transistors TR6 and TR7.
As is illustrated in FIG. 2, three transistors, TR1, TR4 and TR5, may be turned on or off in response to a read enable signal EN-R that is received from an external portion of the device. When the read enable signal EN-R is activated, the transistors TR1, TR4 and TR5 are each turned on, and the data signal carried by the local data I/O line pair LIO/LIOB is amplified by the local sense amplifier LSA and transmitted to the peripheral circuit region 20 through the global data I/O line pair GIO/GIOB.
The two transistors TR6 and TR7 may be turned on or off in response to a write enable signal EN-W that is also received from an external portion of the device. When the write enable signal EN-W is activated, the two transistors TR6 and TR7 are turned on, and thus a data signal received through the global data I/O line pair GIO/GIOB is transmitted to the local gate I/O line pair LIO/LIOB through the local global I/O gate LGIOG
Thus, during a read operation, the local sense amplifier LSA of the semiconductor memory device of FIG. 2 amplifies the data signal carried by the local data I/O line pair LIO/LIOB and transmits the amplified data signal to the peripheral circuit region 20 through the global data I/O line pair GIO/GIOB in response to the read enable signal EN-R. During a write operation, the local global I/O gate LGIOG transmits data received from the peripheral circuit region 20 through the global data I/O line pair GIO/GIOB to the local data I/O line pair LIO/LIOB in response to the write enable signal EN-W.
FIG. 3 is a schematic diagram illustrating the arrangement of a local data I/O line pair LIO/LIOB and a global data I/O line pair GIO/GIOB in the conventional semiconductor memory device. In FIG. 3, LIO/LIOB denotes a local data I/O line pair, GIO/GIOB denotes a global data I/O line pair, WL denotes a word line, CSL denotes a column selecting signal line, LSA denotes a local sense amplifier, and LGIOG denotes a local global I/O gate. Non-cross-hatched lines are lines arranged on a first layer, while cross-hatched lines are lines arranged on a second layer. The arrangement of the local data I/O line pairs LIO/LIOB and the global data I/O line pairs GIO/GIOB in the conventional semiconductor memory device of FIG. 3 is explained below.
The word lines WL and the local data I/O line pairs LIO/LIOB are arranged on the first layer and extend in the same direction. The column selecting signal lines CSL and the global data I/O line pairs GIO/GIOB are arranged on the second layer, and are generally perpendicular to the word lines WL and to the local data I/O line pairs LIO/LIOB.
The conventional semiconductor memory device uses the driver DRV in the peripheral circuit region 20 to drive a data signal and transmit it through the global data I/O line pair GIO/GIOB during a write operation, thereby writing data to the memory cell. The conventional semiconductor memory device uses the local sense amplifier LSA to amplify the data stored in the memory cell and transmit it through the global data I/O line pair GIO/GIOB to the I/O sense amplifier IOSA in the peripheral circuit region 20 where it is sensed during a read operation.